ISL55100BIRZ【PDF 14/14 页】IC COMP DRVR/WINDOW 18V 72-QFN

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Sheet目录2001

10页 11页 12页 13页 [14页]

FN6229.1

November 24, 2008

ground. This same capacitor combination should be placed

at each supply pin to ground if split supplies are to be used.

Power Dissipation Considerations

Specifying continuous data rates, driver loads and driver

level amplitudes are key in determining power supply

requirements as well as dissipation/cooling necessities.

Driver Output patterns also impact these needs. The faster

the pin activity, the greater the need to supply current and

remove heat.

Figures 17 and 18 address power consumption relative to

frequency of operation. These graphs are based on driving

6.0/0.0V out into a 1k

Ω load. Theta JA for the device

package is 23.0, 16.6 and 14.9°C/W based on Airflows of 0,

1 and 2.5 meters per second. The device is mounted per

Note 1 under “Thermal Information” on page 4. With the high

speed data rate capability of the ISL55100B, it is possible to

exceed the +150°C “ absolute maximum junction

temperature” as operating conditions and frequencies

increase. Therefore, it is important to calculate the maximum

junction temperature for the application to determine if

operating conditions need to be modified for the device to

remain in the safe operating area.

The maximum power dissipation allowed in a package is

determined according to Equation 1:

where:

TJMAX = Maximum junction temperature

TAMAX = Maximum ambient temperature

θJA = Thermal resistance of the package

PDMAX = Maximum power dissipation in the package

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the loads.

Power also depends on number of channels changing state,

frequency of operation. The extent of continuous active

pattern generation/reception will greatly effect dissipation

requirements.

The power dissipation curves (Figure 17), provide a way to

see if the device will overheat. The maximum safe power

temperature vs operating frequency can be found

graphically in Figure 18. This graph is based on the package

type Theta JA ratings and actual current/wattage

requirements of the ISL55100B when driving a 1k load with a

6V High Level and a 0V Low Rail. The temperatures are

indicated as calculated junction temperature over the

ambient temperature of the user’s system. Plots indicate

temperature change as operating frequency increases (the

graph assumes continuous operation). The user should

evaluate various heat sink/cooling options in order to control

the ambient temperature part of the equation. This is

especially true if the users applications require continuous,

high speed operation.

The reader is cautioned against assuming the same level of

thermal performance in actual applications. A careful

inspection of conditions in your application should be

conducted. Great care must be taken to ensure Die

Temperature does not exceed the +150°C Absolute

Maximum Thermal Limits.

Important Note: The ISL55100B package metal plane is

used for heat sinking of the device. It is electrically

connected to the negative supply potential (VEE). If VEE

is tied to ground, the thermal pad can be connected to

ground. Otherwise, the thermal pad (VEE) must be

isolated from other power planes.

Power Supply Sequencing

The ISL55100B references every supply with respect to

VEE. Therefore apply VEE, then VCC followed by the VH,VL

busses, then the COMP High and Comp Low followed by the

CVA and CVB Supplies. Digital Inputs should be set with a

differential bias as soon as possible. In cases where VEXT is

being utilized (VEXT = VEE + 5.5V), it should be powered up

immediately after VCC. Basically, no pin should be biased

above VCC or below VEE.

Data Rates

Please note that the Frequency (MHz) in Figures 17 and 18

contain two transitions within each period. A digital

application that requires a new test pattern every 50ns would

be running at a 20MHz Data Rate. Figure 19 reveals 100ns

period, in 10MHz frequency parlance, results in two 50ns

digital patterns.

ESD Protection

Figure 6 is the block diagram depicting the ESD protection

networks and the VOH upper FET body diode.

DMAX

JMAX - TAMAX

---------------------------------------------

(EQ. 1)

ISL55100B

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